Top all-time · #892
Performance Matters
Personal blog · travisdowns.github.io/blogprogrammingsystems
Performance Matters is a personal blog at travisdowns.github.io about programming and systems. Since 2019, 73 different Hacker News readers have linked it 132 times, most often “A Concurrency Cost Hierarchy”. The last post was in 2021, but the archive is still widely read.
Rarely recommended · 4 of 40 sampled comments recommend it?
Why HN links it
HN readers link it for detailed measurements of CPU behaviour, including AVX-512 frequency licensing and downclocking, store forwarding and concurrency costs, citing it as evidence in arguments about Intel and AMD chips.
- Recommended for · 4 comments
- Called great for low-level software; a concurrency post called awesome; register-count work called great; one suggested read that "helps".
Summarised by Claude from a sample of 40 HN comments that link here. Each comment is marked recommending, critical or neutral (citing without judging); how this works.
A blog about low-level software and hardware performance.
Most-linked posts?
- A Concurrency Cost Hierarchy16 people · 29 mentions · first linked 2020-07-06
- Gathering Intel on Intel AVX-512 Transitions11 people · 12 mentions · first linked 2020-01-17
- Ice Lake AVX-512 Downclocking8 people · 12 mentions · first linked 2020-08-19
- Performance Speed Limits7 people · 10 mentions · first linked 2019-06-11
- AVX-512 Mask Registers, Again6 people · 9 mentions · first linked 2020-05-26
- Beating Up on Qsort (2019)6 people · 7 mentions · first linked 2019-05-23
- The Hunt for the Fastest Zero6 people · 6 mentions · first linked 2020-01-20
- Incrementing vectors5 people · 6 mentions · first linked 2019-08-26
- Hardware Store Elimination5 people · 6 mentions · first linked 2020-05-13
- Where do interrupts happen?4 people · 4 mentions · first linked 2019-08-20
What Hacker News says?
This is not true anymore: https://travisdowns.github.io/blog/2020/08/19/icl-avx512-fre...
Comment linking /blog/2020/08/19/icl-avx512-freq.html
on “AMD Zen 3/Ryzen 5000 announcement [video]”Submitted Your CPU may have slowed down on Wednesday as a story · 735 points
HN discussionFrom the post about the original finding ( https://travisdowns.github.io/blog/2020/05/13/intel-zero-opt... ), it looks like Haswell did not have this optimization to begin with (find section Hardware Survey and look at the different architectures - specifically looking for divergence in performance at L3 and RAM between orange and blue dots).
Comment linking /blog/2020/05/13/intel-zero-opt.html
on “Your CPU may have slowed down on Wednesday”Submitted Clang Format Tanks Performance as a story · 306 points
HN discussionFor low-level software, these are great: https://eli.thegreenplace.net/ https://travisdowns.github.io/ https://preshing.com/
Comment linking /
on “Ask HN: What are good solo developer blogs that you enjoy reading?”Submitted Performance Speed Limits as a story · 256 points
HN discussionWell, there was a real-time thing bought by Sun from Sweden but I'm still unclear as to how much of that has made it into the open-source part of the JDK. Time will tell! Joint Parallelism is a term that I invented, it means loosely defined: if two threads can read and write to the same memory at the same time without it causing too much loss... basically you need atomic concurrency which is only really efficient on…
Comment linking /blog/2020/07/06/concurrency-costs.html
on “Why asynchronous Rust doesn't work”Submitted Where do interrupts happen? as a story · 192 points
HN discussionI think this one helps: https://travisdowns.github.io/blog/2020/07/06/concurrency-co...
Comment linking /blog/2020/07/06/concurrency-costs.html
on “Server-Sent Events: an alternative to WebSockets”Submitted A Concurrency Cost Hierarchy as a story · 147 points
HN discussion>On Ice Lake Xeon the penalty for using the AVX-512 features on a single core is -100MHz. That is a penalty due to licensing [0], not thermal throttling. As I wrote elsewhere, I’ve seen my clockspeed get cut in half across all cores on a physical die when running AVX-heavy operations for a sustained period of time, due to thermal throttling. [0] https://travisdowns.github.io/blog/2020/08/19/icl-avx512-fre...
Comment linking /blog/2020/08/19/icl-avx512-freq.html
on “Vectorized and performance-portable Quicksort”Submitted The Hunt for the Fastest Zero as a story · 133 points
HN discussion> Slow compiles are an issue with C++ templates. As far as I know Rust has the same problem although to lesser extent. Monomorphization works well with judicious use. C++ STL is not written like that, they depend on 11111 layers of inlining to work well. Rust libraries aren't much better in this regard. LTO removed some code bloat, but LTO itself takes more time. until thinLTO summary pass / equivalent pass in GCC W…
Comment linking /blog/2020/01/20/zero.html
on “Generics can make your Go code slower”Submitted Ice Lake AVX-512 Downclocking as a story · 126 points
HN discussionNo, actually grandparent is correct here - Skylake-X/Skylake-SP have never clocked down the first time they see an AVX-512 instruction. It actually is when the AVX instructions start to get dense enough to justify a voltage swing upwards. This actually exists in Haswell as well - certain AVX2 instructions are designated "heavy" and if you get enough of them you'll enter a voltage or frequency transition. On Skylake-…
Comment linking /blog/2020/08/19/icl-avx512-freq.html
on “Zen4's AVX512 Teardown”Submitted Gathering Intel on Intel AVX-512 Transitions as a story · 126 points
HN discussionThat was before Ice Lake, where it had a very decent performance (just downclocking 10%) and then on Rocket Lake it didn't even downclock [0]. But the thing that stuck in our collective mind was that "it's bad because it downclocks". And seeing the RKL numbers, which are new to me (I had only read de Ice Lake numbers back in 2020) it wasn't even 14nm's fault, just an implementation issue which Intel eventually worke…
Comment linking /blog/2020/08/19/icl-avx512-freq.html
on “Intel completely disables AVX-512 on Alder Lake after all”Submitted AVX-512 Mask Registers, Again as a story · 102 points
HN discussionIt’s not the instruction decoder that wastes die space. In fact, it’s less than 5% of the die (on Skylake).[0] [0]: https://pbs.twimg.com/media/EXFJLebXkAYkXTr?format=jpg&name=... In case that link dies, it’s from [1] which is linked from [2] [1]: https://mobile.twitter.com/GPUsAreMagic/status/1256866465577... [2]: https://travisdowns.github.io/blog/2020/05/26/kreg2.html
Comment linking /blog/2020/05/26/kreg2.html
on “Apple M1 vs. Ryzen 3900X vs. Intel I9 in Software Development”Submitted Incrementing vectors as a story · 98 points
HN discussionThe operations are somewhat different though. Store-to-load forwarding is more complicated and doesn't completely eliminate the operation, it just significantly reduces the cycle count when successful. Although apparently Zen 2 changed this and can pull off zero latency. ( https://www.agner.org/forum/viewtopic.php?t=41 ) Some general background: ( https://travisdowns.github.io/blog/2019/06/11/speed-limits.h... )
Comment linking /blog/2019/06/11/speed-limits.html
on “Nvidia Unveils Grace: A High-Performance Arm CPU for Use in Big AI Systems”Submitted Ice Lake Store Elimination as a story · 97 points
HN discussionThe only problem Java has is experienced C programmers don't build servers from scratch with it yet. Once they take that responsibility, the debate will be over because: "While I'm on the topic of concurrency I should mention my far too brief chat with Doug Lea. He commented that multi-threaded Java these days far outperforms C, due to the memory management and a garbage collector. If I recall correctly he said "onl…
Comment linking /blog/2020/07/06/concurrency-costs.html
on “Don’t call it a comeback: Java is still champ”Submitted What has your microcode done for you lately? as a story · 90 points
HN discussion"While I'm on the topic of concurrency I should mention my far too brief chat with Doug Lea. He commented that multi-threaded Java these days far outperforms C, due to the memory management and a garbage collector. If I recall correctly he said "only 12 times faster than C means you haven't started optimizing"." - Martin Fowler https://martinfowler.com/bliki/OOPSLA2005.html "Many lock-free structures offer atomic-fr…
Comment linking /blog/2020/07/06/concurrency-costs.html
on “Chip design shifts as fundamental laws run out of steam”Submitted Beating Up on Qsort (2019) as a story · 81 points
HN discussionYou have to switch to a higher-voltage state to account for the voltage droop that you will cause when the AVX units fire off. https://travisdowns.github.io/blog/2020/01/17/avxfreq1.html (specifically: https://travisdowns.github.io/assets/avxfreq1/fig-volts256-1... ) > So one theory is that this type of transition represents the period between when the CPU has requested a higher voltage (because wider 256-bit instru…
Comment linking /assets/avxfreq1/fig-volts256-1.svg
on “AMD Threadripper 3970X under heavy AVX2 load: Defective by design?”Submitted Incrementing Vectors (2019) as a story · 48 points
HN discussionNot increased number of execution units, but increased number of transistors, yeah. A normal multiply does 1 number at a time (32 bit for simplicity). AVX2 can do up to 8 multiplications at a time. That's a huge amount more transistors firing all at once and that causes the voltage to start to droop. AVX-512 takes that even further and now it's 16 multiplications per unit, oh and Intel moved from 1x256-bit unit per…
Comment linking /assets/avxfreq1/fig-volts256-1.svg
on “AMD Threadripper 3970X under heavy AVX2 load: Defective by design?”Submitted Hardware Store Elimination as a story · 45 points
HN discussion
