Top all-time · #132
Agner Fog
Personal blog · agner.orgprogramminghardwaresystems
Agner Fog's personal blog at agner.org covers programming, hardware and systems. Since 2009, 296 different Hacker News readers have linked it 423 times, most often “List of latencies, throughputs and micro-operations for Intel, AMD, and VIA CPUs [pdf]”. No feed was found, so read it on the site itself.
Sometimes recommended · 9 of 40 sampled comments recommend it?
Why HN links it
HN readers link Agner Fog's optimization manuals and instruction tables as the standard reference for x86 CPU microarchitecture, latencies and performance, and cite his blog on compilers crippling AMD performance.
- Recommended for · 9 comments
- Commenters call Agner Fog's manuals 'the bible' and 'mind blowingly awesome', and one says his optimization resources are the best place to start.
Summarised by Claude from a sample of 40 HN comments that link here. Each comment is marked recommending, critical or neutral (citing without judging); how this works.
Agner Fog's research. Topics: Cultural evolution - Evolutionary anthropology - Simulation of biological evolution - Software optimization - Random number generators
Most-linked posts?
- List of latencies, throughputs and micro-operations for Intel, AMD, and VIA CPUs [pdf]42 people · 49 mentions · first linked 2018-08-26
- Software optimization resources for C++, assembly, Windows, Linux, BSD, Mac OS33 people · 36 mentions · first linked 2018-08-26
- Software optimization resources25 people · 30 mentions · first linked 2010-02-16
- An optimization guide for assembly programmers and compiler makers (2018) [pdf]22 people · 28 mentions · first linked 2018-10-01
- The Microarchitecture of Intel, AMD and VIA CPUs [pdf]17 people · 20 mentions · first linked 2010-05-25
- Instruction latencies, throughputs, μop breakdowns for Intel, AMD and VIA CPUs [pdf]17 people · 19 mentions · first linked 2013-11-30
- Optimization Manuals13 people · 13 mentions · first linked 2018-10-13
- /optimize/blog/read.php?i=4911 people · 12 mentions · first linked 2019-11-25
- Optimizing Software in C++ [pdf]9 people · 9 mentions · first linked 2011-10-30
- Intel's "cripple AMD" function (2009)9 people · 9 mentions · first linked 2010-01-03
What Hacker News says?
It doesn't seem that this affects wall time for a single addition though, at least on typical x86 CPUs. If you look at Agner's performance tables [1], ADD instructions always take the same number of cycles. I'm not a hardware expert, but I'm guessing that what's happening here is that transistors get hotter with certain input values more than others. Eventually this results in higher overall CPU temperature and a lo…
Comment linking /optimize/instruction_tables.pdf
on “Hertzbleed Attack”Submitted Intel's “cripple AMD” function (2019) as a story · 500 points
HN discussion> This means that, on modern processors, the same program can run at a different CPU frequency (and therefore take a different wall time) when computing, for example, 2022 + 23823 compared to 2022 + 24436. I'm not a hardware expert, and I was a bit surprised at this. Is that because the transistors heat up more with certain input values, which then results in a lower frequency when the CPU gets hot enough? Something…
Comment linking /optimize/instruction_tables.pdf
on “Hertzbleed Attack”Submitted Surprising new feature in AMD Ryzen 3000 as a story · 411 points
HN discussionA contributing factor is how complex/smart the current hardware is. It can have cache line size, different forms of hardware/software prefetching, different ports for different ops, memory latency, simd extensions. These leave many opportunities for algorithms to be optimized over. There is also the issue of real life scenarios not matching with asymptotic ones (due to e.g., size of input), which when coupled with p…
Comment linking /optimize/
on “Undergraduate shows that searches within hash tables can be much faster”Submitted Intel's "cripple AMD" function (2009) as a story · 356 points
HN discussion* Donald Knuth's "Art of Computer Programming" * Jon Kleinberg, Eva Tardos's "Algorithm Design". * Paul Horowitz's "The Art of Electronics" * Agner Fog's "Microarchitecture of Intel, AMD, and VIA CPUs": https://www.agner.org/optimize/microarchitecture.pdf Not a big list, and I've got a lot of textbooks. Knuth's writing style is difficult, its the hardest read I've ever had. But Knuth hits you with the hardest exampl…
Comment linking /optimize/microarchitecture.pdf
on “Ask HN: What are the best textbooks in your field of expertise?”Submitted Intel's “Cripple AMD” Function (2019) as a story · 294 points
HN discussionSorry, nothing else in this genre comes to mind. There is always Agner Fog's optimization resources which are mind blowingly awesome if you worry about the performance of your C or C++ code like I do - his site is in https://www.agner.org/ and the optimization manuals are in https://www.agner.org/optimize/#manuals (I suggest starting from optimizing_cpp.pdf)
Comment linking /optimize/
on “Ask HN: Favorite Blogs by Individuals?”Submitted An optimization guide for assembly programmers and compiler makers (2018) [pdf] as a story · 271 points
HN discussionVery much true. REP SCASB on 1994 (same year as the incident in the article) Intel Pentium would have taken 9 + 4 * n clock cycles [0][1] to go through a string. So scanning 4 chars long string takes 25 clock cycles. [0]: Agner's instruction tables page 123: https://www.agner.org/optimize/instruction_tables.pdf [1]: Plus one extra cycle to decode REP prefix, if previous instruction took 1 cycle.
Comment linking /optimize/instruction_tables.pdf
on “New Grad vs. Senior Dev”Submitted Intel's New Chimera: Alder Lake as a story · 264 points
HN discussionOK, I could see how one could implement a variable width instruction decoder (e.g. "if there are 8 one-byte instructions in a row, handle them, otherwise fallback to 4-way decoding" -- of course much more sophisticated approach could be made). But is this actually done? I honestly would be interested in a source for that; I just searched again and could find no source supporting this (but of course I may have simply…
Comment linking /optimize/microarchitecture.pdf
on “Why is Apple's M1 chip so fast?”Submitted Test Results for AMD Zen 5 as a story · 255 points
HN discussionRead Agner Fog's optimisation manuals. https://www.agner.org/optimize/#manuals
Comment linking /optimize/
on “Overhauling Mario 64's code to reach 30 FPS and render 6x faster on N64 [video]”Submitted Intel's "cripple AMD" function as a story · 212 points
HN discussion>A) it can run another hyperthread with those cycles, and, I don't see hyperthreading useful. Neither do the benchmarks, that usually put hypterthreading off ahead of hypterthreading on. Reasoning is simple. When a cache miss happens the (intel) cpu runs another thread. The question is does that happen often enough to justify the overhead of that "hyper"threading. Remember that hyperthreading does not magically make…
Comment linking /optimize/blog/read.php?i=6
on “CPU Utilization is Wrong”Submitted The Microarchitecture of Intel, AMD and VIA CPUs [pdf] as a story · 205 points
HN discussion> either via function pointers or a switch/if? > but would a modern CPU not be able to predict the path taken by a brach that tests the CPU features. That's true, but the CPU has finite branch predictor state, and now you've wasted some of it. Indirect calls hurt too, especially in you need retpolines. This is a great read: https://www.agner.org/optimize/microarchitecture.pdf The Linux kernel has interfaces for doin…
Comment linking /optimize/microarchitecture.pdf
on “The xz attack shell script”Submitted Software optimization resources for C++, assembly, Windows, Linux, BSD, Mac OS as a story · 172 points
HN discussionIf you want to get technical, modern CPUs can dispatch (begin the execution) of 4 to 6 instructions every clock cycle. However, many instructions take more than one cycle to complete. For instance, integer multiply takes 3-4 cycles on an Intel Sandy Bridge chip. FMUL takes 5 cycles to complete. That being said, there are several instructions, like mov, integer additions and compare, bitwise operations, which can abs…
Comment linking /optimize/instruction_tables.pdf
on “How much your computer can do in a second”Submitted Agner Fog as a story · 165 points
HN discussionWhy are scene coders more correct than other coders. If Agner Fog has no problem calling it 'assembly'[0], then neither do I. 0: http://agner.org/optimize/
Comment linking /optimize/
on “GodBolt: Enter C, get Assembly”Submitted Low-level details of the Zen 2 microarchitecture [pdf] as a story · 163 points
HN discussionWhat I also find rather interesting is the concept of macro-op fusion that Intel introduced with the Core 2 processors: This means for example that a cmp ... (or test ...) followed by a conditional jump can/will be fused together to a single micro-op. In other words: Suddenly a sequence of two instruction maps to one internal micro-op. If you are interested in the details, read section 8.5 in http://www.agner.org/op…
Comment linking /optimize/microarchitecture.pdf
on “Learning to Read X86 Assembly Language”Submitted Moore's law hits the roof as a story · 150 points
HN discussionExactly the opposite is correct. ICC generated code whose runtime dispatch looked at "Are we running on Intel? Select fast path. Not running Intel? Select generic i386 path." http://www.agner.org/optimize/blog/read.php?i=49#49
Comment linking /optimize/blog/read.php?i=49
on “AMD Zen and Ryzen 7 Review: A Deep Dive”Submitted Software optimization resources as a story · 115 points
HN discussionIntel provides a lot of tools and SDKs for game developers. I presume some/many are specifically optimized and highly-tuned for running best on Intel processors: https://software.intel.com/en-us/gamedev/ But also things like physics engines (eg. Havok, which was acquired by Intel and heavily optimized for Intel processors), etc. And of course Intel's C Compiler is known to cripple AMD: http://www.agner.org/optimize/…
Comment linking /optimize/blog/read.php?i=49
on “AMD Zen and Ryzen 7 Review: A Deep Dive”Submitted Future instruction set: AVX-512 as a story · 102 points
HN discussion
